پاورپوینت Architectural Analysis of a DSP Device, the Instruction Set and the Addressing Modes

دانلود پاورپوینت Architectural Analysis of a DSP Device the Instruction Set and the Addressing Modes بررسی Architectural Analysis of a DSP Device the Instruction Set and the Addressing Modes پاورپوینت جامع و کامل Architectural Analysis of a DSP Device the Instruction Set and the Addressing Modes

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کد کاربری 8044

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نوع فایل: پاورپوینت (قابل ویرایش)

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تعداد اسلاید : 50 صفحه

1 Architectural Analysis of a DSP Device, the Instruction Set and the Addressing Modes SYSC5603 (ELG6163) Digital Signal Processing Microprocessors, Software and Applications

Miodrag Bolic

2 Outline FIR filter on ADPS-21x

DSP Requirements
Fast Multiply-Accumulates (Data-path)
Extended Precision Accumulator Register (Data-path)
Dual Operand Fetch (Memory)
Circular Buffering (Addressing)
Zero-Overhead Looping (Instruction set)

Analog Devices Architectures and Programming
SHARC
Blackfin
Performance Optimization
3 ADSP -21x Copied from [Kester03] 4 CALCULATING OUTPUTS OF 4-TAP FIR FILTER USING A CIRCULAR BUFFER y(3) = h(0) x(3) + h(1) x(2) + h(2) x(1) + h(3) x(0) y(4) = h(0) x(4) + h(1) x(3) + h(2) x(2) + h(3) x(1) y(5) = h(0) x(5) + h(1) x(4) + h(2) x(3) + h(3) x(2) Memory
Location

0

1

2

3 Read

x(0)

x(1)

x(2)

x(3) Write

x(4)





Read

x(4)

x(1)

x(2)

x(3) Write



x(5)



Read

x(4)

x(5)

x(2)

x(3) Copied from [Kester03] 5 FIR filter steps 1. Obtain a sample with the ADC; generate an interrupt
2. Detect and manage the interrupt
3. Move the sample into the input signal's circular buffer
4. Update the pointer for the input signal's circular buffer
5. Zero the accumulator
6. Control the loop through each of the coefficients
7. Fetch the coefficient from the coefficient's circular buffer
8. Update the pointer for the coefficient's circular buffer
9. Fetch the sample from the input signal's circular buffer
10. Update the pointer for the input signal's circular buffer
11. Multiply the coefficient by the sample
12. Add the product to the accumulator
13. Move the output sample (accumulator) to a holding buffer
14. Move the output sample from the holding buffer to the DAC

Copied from [Kester03] 6 FIR filter steps (cont.) ADSP21xx Example code:

CNTR = N-1;
DO convolution UNTIL CE;
convolution:
MR = MR + MX0 * MY0(SS), MX0 = DM(I0,M1), MY0 = PM(I4,M5); Copied from [Kester03] 7 Outline FIR filter on ADPS-21x

DSP Requirements
Fast Multiply-Accumulates (Data-path)
Extended Precision Accumulator Register (Data-path)
Dual Operand Fetch (Memory)
Circular Buffering (Addressing)
Zero-Overhead Looping (Instruction set)

Analog Devices Architectures and Programming
SHARC
Blackfin
Perform

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دانلود پاورپوینتArchitectural Analysis of a DSP Device the Instruction Set and the Addressing ModesبررسیArchitectural Analysis of a DSP Device the Instruction Set and the Addressing Modesپاورپوینت جامع و کاملArchitectural Analysis of a DSP Device the Instruction Set and the Addressing Modes